USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
| RXTHINTCLR | Receive FIFO Threshold Interrupt clear. |
| TXTHINTCLR | Transmit FIFO Threshold Interrupt clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTIMEOUTINTCLR | Receive FIFO Time-out Interrupt clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXFLUSHCLR | Receive FIFO flush clear. |
| TXFLUSHCLR | Transmit FIFO flush clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |